BiCMOS integrated circuits contain both bipolar and MOS transistors. In a typically used BiCMOS fabrication process, the Nwell doping profile is determined by constraints on both the PMOS and NPN devices. PMOS device requirements that may affect the doping profile of the Nwell include source/drain punch through voltage, latch up immunity, moat-moat punch through isolation threshold voltage, and Nwell-substrate breakdown voltage. Often, in satisfying these requirements for PMOS devices, the related performance of NPN bipolar devices is sacrificed. Specifically, NPN transistors may suffer from degraded performance in terms of base-collector breakdown voltage, base-collector junction capacitance, and/or collector current density.